Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
Although the need for increased communication bandwidth continues to drive future designs, adaptability also remains as a high priority goal. As such, the future designs are required to provide a wide range of scalability, whereby many of the physical (PHY) layer attributes are adaptable to the various requirements of emerging serial communication protocols.
For example, an input buffer utilized in the implementation of a particular serial communication interface may be required to adapt to either of a direct current (DC) coupled or alternating current (AC) coupled mode of operation. If an AC coupled mode of operation is selected, for example, then substantially all of the low frequency variations of the input signal are filtered, i.e., attenuated, prior to being transferred to the input buffer. Conversely, if a DC coupled mode of operation is selected, then substantially all of the low frequency variations of the input signal are left undisturbed, whereby the full bandwidth of the input signal is applied to the input buffer.
Given that a DC coupled mode of operation is selected, however, an additional design consideration is typically placed on the transmitting end of the transmitter/receiver pair. In particular, the transmitter is often required to maintain the common mode component of the transmitted signal: 1) within a narrow range of variation; and 2) within close proximity to a fixed DC potential, such as ground potential. As such, design constraints on the transmitter may be excessively and unnecessarily imposed.
Another design constraint that may be imposed upon the transmitter/receiver pair is the maintenance of compatibility across the various generations of logic families used to implement the transmitter/receiver pair. A particularly popular logic family that is often utilized, especially for those transmitter/receiver pairs that employ differential serial communications, is current mode logic (CML). CML is typically employed in one of two variations: 1) top-rail power supply referenced CML; and 2) bottom-rail power supply referenced CML.
The top-rail power supply, e.g., VDD, referenced CML family provides an output logic level, whose output logic high level, VOH, is substantially equal to VDD and whose output logic low level, VOL, is substantially equal to VDD minus the product of the tail current and the load resistance as described by equation (1):VOL=VDD−ITAIL*RLOAD.  (1)The common mode voltage of the VDD-referenced CML logic family, VCM−VDD, is calculated to be one-half of the output voltage swing as described by equation (2):
                              V                      CM            -            VDD                          =                                            (                                                V                  OH                                -                                  V                  OL                                            )                        2                    =                                                    (                                                      V                    DD                                    -                                      (                                                                  V                        DD                                            -                                                                        I                          TAIL                                                *                                                  R                          LOAD                                                                                      )                                                              2                        .                                              (        2        )            
Conversely, the bottom-rail power supply, e.g., VSS, referenced CML family provides an output logic level, whose output logic low level, VOL, is substantially equal to VSS and whose output logic high level, VOH, is substantially equal to VSS plus the product of the head current and the load resistance as described in equation (3):VOH=VSS+IHEAD*RLOAD.   (3)The common mode voltage of the VSS-referenced CML logic family, VCM−VSS, is calculated to be one-half of the output voltage swing as described by equation (4):
                              V                      CM            -            VSS                          =                                            (                                                V                  OH                                -                                  V                  OL                                            )                        2                    =                                                                      (                                                            V                      SS                                        +                                                                  I                        HEAD                                            *                                              R                        LOAD                                                                              )                                -                                  V                  SS                                            2                        .                                              (        4        )            
Comparing equation (4) with equation (2), it can be seen that VCM−VSS does not depend upon the top-rail power supply, e.g., VDD. More particularly, VCM−VSS is referenced to the bottom-rail power supply, VSS, which is typically equal to ground potential. In such an instance, therefore, VCM−VSS is substantially independent of VDD variations across the various generations of CML families and is, therefore, preferred. On the other hand, it can be seen that VCM−VDD of equation (2) is directly proportional to VDD and hence, is directly affected by VDD variations across the various generations of CML families.
Thus, as the design constraints across future generations of CML families force the level of VDD to decrease, the value of VCM−VDD also decreases in direct proportion, as described by equation (2). While this inherent characteristic of VDD-referenced CML may not be detrimental in an AC coupled mode of operation, variations in VCM−VDD may nevertheless be detrimental in a DC coupled mode of operation. Particularly when the VCM−VDD voltage approaches the value of VSS, e.g., ground potential. In this instance, a typical VDD-referenced CML receiver, employing for example, N-type field effect transistors (FETs), may be disabled by such a VCM−VDD characteristic.
Accordingly, the exemplary schematic of input buffer 100 of FIG. 1 may be employed, to provide an AC coupled mode of operation that alleviates the problems discussed above in relation to variations of VCM−VDD across multiple generations of CML families. Furthermore, provisions are also made to accommodate the requisite VCM−VDD characteristic, as discussed above in relation to the N-type FET based, VDD-referenced CML receiver, during an AC coupled mode of operation. Disclosure relating to the exemplary embodiment of FIG. 1 is presented in detail by U.S. patent application Ser. No. 10/659,971 entitled “RECEIVER TERMINATION NETWORK AND APPLICATION THEREOF,” by Boecker et al., having a filing date of Sep. 11, 2003, and assigned to the assignee of the present invention, the content of which is incorporated herein by reference.
In operation, a differential signal is received by input buffer 100 at nodes INP and INN, which is transmitted by a transmitter (not shown) through a transmission channel (not shown). Resistors 102 and 104 represent impedance matching resistors that may be employed in a double terminated transmission channel. That is to say, for example, that an equivalent resistive network is provided at the transmitter, whereby the termination at the transmitter and the termination provided by resistors 102 and 104 are impedance matched to the characteristic impedance of the transmission channel being used, e.g., 50 ohms.
Switches 118 and 120 are closed during a DC mode of operation, since closure of switches 118 and 120 places a short circuit across capacitors 106 and 108, respectively. Conversely, switches 118 and 120 are left open during an AC mode of operation. In such an instance, resistor/capacitor (RC) filter 110/106 and RC filter 112/108 operate as high-pass filters to prevent low-frequency content, injected at nodes INP and INN, from affecting the conductivity state of transistors 114 and 116.
By injecting a programmable, common mode voltage at nodes 122 and 124, a dual mode of operation of input buffer 100 is accomplished. That is to say, for example, that switches 118 and 120 may be left open to allow RC filters 110/106 and 112/108 to block any low frequency components that may exist at nodes INP and INN. At the same time, a programmable common mode voltage, VCM, may be injected at nodes 122 and 124 via bias resistors 110 and 112 in order to bias transistors 114 and 116 into a proper conductivity state. In this way, input buffer 100 is AC coupled between nodes INP and 122 and between nodes INN and 124, while at the same time, maintaining a proper DC bias at the control inputs of transistors 114 and 116 via programmable common mode voltage, VCM.
In certain communication systems, however, the communication protocol requires a physical layer that remains DC coupled, while simultaneously operating at a common mode voltage at or near ground potential. An example of such a protocol is illustrated by the Fully Buffered Dual In-Line Memory Module (FB-DIMM) specification, whereby the FB-DIMM operates as a memory device that maintains a very low duty cycle on its data lines.
As such, the FB-DIMM compliance specification requires DC coupling in order to prevent the “bleeding away” of data levels on those data lines. Turning back to FIG. 1, it can be seen that the closure of switches 118 and 120 provides the requisite DC coupling for FB-DIMM compliance. The common mode voltage, however, that exists at nodes 122 and 124 during the DC mode of operation is most likely insufficient to properly bias transistors 114 and 116 into a conductive state, since the common mode voltage necessary for FB-DIMM compliance is substantially equal to VSS.
Improvements continue to be developed, therefore, to allow wide variations in the common mode input voltage without degrading the performance of a DC coupled input buffer. The AC mode of operation should also be enhanced, whereby proper sampling of the input data may be facilitated despite the existence of DC imbalances, prolonged periods of data inactivity, and large variations in common mode voltages at the input nodes of an input buffer.